Principal/Lead ASIC Design and Verification Engineer – £130k – Oxford

Due to our continued growth, our semiconductor client is looking for an Principal/Lead ASIC Design and Verification Engineer (50/50 Hands on and Team Management)  to join their cutting-edge SoC team in the development of ASICs. The successful candidate will be working with experts in different aspects of SoC development on state of the art projects.

You will be given the opportunity to undertake role specific training to further develop your knowledge, experience and further your career development.

The successful candidate will also be working directly for an industry renowned Senior Director who has built and established many multi-discipline teams throughout their career and his teams have enjoyed major success

This team is going to be a pure multidiscipline team which can tackle any issue that comes there way and become some of the industries most well-rounded engineers.

Principal/Lead ASIC Design and Verification Engineer Expected contributions:

• Mentoring and Guiding Engineers and Peers
• Collaborating with Senior Principal Engineers
• Expert level Understanding of different parts of the design & verification cycle.
• Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal).
• Working on high volume data centre & enterprise products used by industry leading Companies.
• Experience of working on projects with teams located internationally.

Principal/Lead ASIC Design and Verification Engineer qualifications and skills:

• 15-20+ years of digital ASIC design and verification experience
• Vast experience of:
  • Translating design requirements into RTL
  • Deriving functional requirements for verification
  • Systemverilog UVM test benches
  • Scripting languages & REST API’s (e.g. Perl/Python/TCL)
• Team player with good verbal and written communication skills

Principal/Lead ASIC Design and Verification Engineer Desirable skills:

• Experience of Formal Verification (Jasper Gold or VC_Formal)
• Experience using SV UVM 1800.2
• Familiarity with C/C++
• Experience with any of the following storage interfaces: SAS, PCIe, NVMe (preferred) or SATA

Salary and Package:

• Competitive Salaries Ranging From £95,000 – £130,000 (Depending on Level and experience)
• 10%-20% Bonus (based on Company and individual performance)
• 25 days holiday + 8 days Bank Holiday per year.
• 3 Days a week on Site hybrid working
• Pension (matched group pension up to 8%)
• Life Assurance
• Income Protection
• Private Medical
• Employee Supported Volunteering
• Employee Assistance Program for Health Well-being, Financial services, Legal services etc
• Training and Development
• Visa Sponsorship available
• Relocation Support (if required)

My client can offer a 3-stage process consisting of a 1^st stage Video Call , 2^nd Stage Video Call and a 3rd Stage on-site Interview (meet the team and site tour). This process can be completed within 2-3 weeks (based on availability)