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Backend Physical Design Engineer – £95k – Farnborough

Backend Physical Design Engineer – £95k – Farnborough

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  • Permanent - Hybrid Working
  • Farnborough

Elite People Partners Ltd

Backend Physical Design Engineer – £95k – Farnborough

Due to our continued growth, Our space client is looking for an Backend Physical Design Engineer to join their Satellite Physical Design team in Farnborough.

This is a fantastic opportunity for someone with a professional background in COT/ASIC physical design flow looking to take the next step in their career and be part of exciting and innovative projects in space.

Be part of a dynamic and motivated multi-national Physical Design team, taking part in developing a state of the art Satellite SoC through the full life cycle: design to production. The chips include complex digital and analog modules. Some of the products are part of the next generation radiation hardened satellite modems. You will have access to best in class EDA design tools and will be working in leading edge process technologies.

Backend Physical Design Engineer – Responsibilities

  • Physical implementation of complex SoC, VLSI devices and Test Chips, integrating custom designs and 3rd party IP (Hard, Soft, IO, CPUs, DSPs, etc)
  • Full block level timing closure and manufacturing checks signoff including power planning and analysis
  • Working alongside the Logic Design RTL team to develop timing constraints for implementation at block and chip level
  • Insertion of DFT test structures and chip level integration, capture and simulation
  • Jointly with management, build your career development and growth opportunities.

Backend Physical Design Engineer – Essential Skills

  • COT/ASIC physical design flow covering: Synthesis, Floorplanning, Place and Route (P&R), Clock Tree Synthesis (CTS), Parasitic Extraction, Static Timing Analysis (STA) and Timing Closure, Physical Verification, Power Analysis, Formal Verification, DFT/DFM and ATPG insertion/pattern generation
  • Deep sub-micron (28nm or below) process technologies
  • Industry standard design processes for deep sub-micron designs
  • Problem-solving and analytical skills
  • Practical use of scripting languages Tcl/Python/Perl etc
  • Experience of at least one of the following EDA tool flows: Cadence or Synopsys
  • Communicating with other design teams, 3rd party IP and library suppliers and EDA tool vendors to improve scripts and tool flow
  • Managing/Interfacing to sub-contract design service providers


  • Competitive base salary (£80k-£95k)
  • 25 days holiday (increasing yearly up to a maximum of 28 days) + 8 days Bank Holiday per year.
  • Pension (Royal London) 3% Employee 5% Employee
  • Hybrid working available (3 days on site, 2 from home)
  • Life insurance
  • Private healthcare
  • Long Term Sick and Disability Cover
  • Visa sponsorship for employees if required
  • Bonus for Security Clearance (SC/DV) Clearance

My client can offer a 2-stage process consisting of a 1st stage Video Call and a 2nd Stage  will be on onsite Technical interview. This process can be completed within 1 week (based on availability)

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