Senior Design Engineer (SystemVerilog / RTL) – £60,000–£80,000 + bonus

My client’s engineering team is looking to add Senior Design Engineers to support the development of next-generation GPU / AI compute IP.

This role is focused on strong RTL engineers who can take ownership of implementation while developing exposure to micro-architecture and broader design considerations.

You will work closely with Staff and Principal engineers, contributing to high-quality design delivery across complex SoC environments.

Senior Design Engineer – Role & Responsibilities:

• Develop high-quality SystemVerilog RTL from defined specifications
• Contribute to block-level design within GPU / compute architectures
• Work closely with verification teams to ensure design correctness and coverage
• Support integration and debug activities across the design flow
• Collaborate with physical design teams to understand implementation constraints
• Participate in design reviews and technical discussions
• Build understanding of micro-architecture decisions and trade-offs

Senior Design Engineer – Essential Skills:

• Strong experience in SystemVerilog or Verilog RTL design
• ~5–10 years’ experience within digital design (SoC / ASIC environments)
• Solid understanding of RTL design principles and coding standards
• Awareness of verification methodologies and simulation flows
• Exposure to physical design considerations (timing, area, power)
• Experience working within cross-functional engineering teams
• Strong problem-solving ability and attention to detail

Nice to Have:

• GPU / CPU / AI accelerator experience
• Memory / cache / interconnect design
• Datapath / ALU / compute block experience
• Experience within high-performance SoC environments

What this isn’t:

• Not a graduate or entry-level role
• Not limited to isolated RTL tasks without broader context
• Not a purely verification-focused position
• Not a role with no progression or technical growth

Why This Role:

• Opportunity to work on complex GPU / AI compute designs
• Exposure to experienced Principal and Staff engineers
• Clear progression path into Staff / architecture roles
• Strong technical environment with real design challenges
• Immediate involvement in active silicon programmes

Salary and Package:

• £60,000 – £80,000 base salary
• 30% Bonus (company performance related)
• Pension
• Private medical
• Life assurance
• Income protection
• Relocation support available
• Hybrid working (3 days onsite)

Interview Process:

My client can offer a 3-stage process consisting of:

• 1st stage: Technical screening (45 minutes)
• 2nd stage: Technical panel (2 hours 10 minutes)
• 3rd stage: HR / final discussion

This process can typically be completed within 2–3 weeks (depending on availability)