Staff Design Engineer (SystemVerilog / Micro-Architecture) – £80,000–£100,000 + bonus

My client’s engineering team is looking to add Staff Design Engineers to support the development of next-generation GPU / AI compute IP.

This role sits at the core of design execution, focused on engineers who can bridge architecture and implementation — taking ownership of block-level design while contributing to broader micro-architecture decisions.

You will work across architecture, RTL design, and physical implementation awareness, collaborating closely with verification and system teams to ensure high-quality, scalable silicon delivery.

Staff Design Engineer – Role & Responsibilities:

• Own block-level design from specification through to RTL implementation
• Contribute to micro-architecture definition alongside Principal / Architect-level engineers
• Develop high-quality SystemVerilog RTL aligned to performance, power, and area targets
• Work closely with verification teams to ensure efficient validation of designs
• Collaborate with physical design teams to understand timing, congestion, and power constraints
• Take ownership of key design blocks within GPU / compute architectures
• Support design reviews and technical discussions across teams
• Operate as a strong individual contributor within a cross-functional engineering environment

Staff Design Engineer – Essential Skills:

• Strong experience in SystemVerilog RTL design
• Experience contributing to micro-architecture (not purely implementation)
• ~10–15 years’ experience within digital design (SoC / CPU / GPU / ASIC environments)
• Understanding of physical design trade-offs (timing, area, power)
• Awareness of verification methodologies and design-for-test principles
• Experience working across architecture, verification, and physical design teams
• Ability to operate independently while collaborating with senior engineers
• Strong communication skills within technical teams

Nice to Have:

• GPU / CPU / AI accelerator experience
• Memory / cache / interconnect design
• Datapath / ALU / compute block experience
• Experience within high-performance SoC environments

What this isn’t:

• Not a pure RTL “coding” role without context
• Not a junior or heavily guided design position
• Not limited to narrow implementation tasks only
• Not a role where all architecture decisions are predefined

Why This Role:

• Opportunity to own meaningful design blocks within complex GPU / AI compute systems
• Exposure to both architecture and implementation challenges
• Work within a collaborative, cross-functional engineering environment
• Clear path toward Principal-level progression
• Immediate impact on active design programmes

Salary and Package:

• £80,000 – £100,000 base salary
• 30% Bonus (company performance related)
• Pension
• Private medical
• Life assurance
• Income protection
• Relocation support available
• Hybrid working (3 days onsite)

Interview Process:

My client can offer a 3-stage process consisting of:

• 1st stage: Technical screening (45 minutes)
• 2nd stage: Technical panel (2 hours 10 minutes)
• 3rd stage: HR / final discussion

This process can typically be completed within 2–3 weeks (depending on availability)