Principal Design Engineer (SystemVerilog / Micro-Architecture) – £95,000–£110,000 + bonus

My client’s engineering team is looking to add Principal Design Engineers to support the development of next-generation GPU / AI compute IP.

This role is focused on strengthening core design and micro-architecture capability, with a clear objective of unblocking delivery across critical programmes where design is currently the constraint.

You will operate at the intersection of architecture, RTL design, and physical implementation awareness, working closely with verification and system teams to ensure scalable, high-performance silicon delivery.

Principal Design Engineer – Role & Responsibilities:

• Own micro-architecture definition from high-level specifications
• Develop high-quality SystemVerilog RTL aligned to performance, power, and area targets
• Work closely with verification teams to ensure design-for-verification efficiency
• Collaborate with physical design teams to understand and mitigate timing, congestion, and power challenges
• Contribute to overall design strategy and technical direction
• Take ownership of complex blocks within GPU / compute architectures
• Support and influence engineering best practices across the design function
• Operate as a senior technical contributor within a matrix engineering structure

Principal Design Engineer – Essential Skills:

• Strong experience in SystemVerilog RTL design
• Proven background in micro-architecture ownership (not just implementation)
• ~15+ years’ experience within digital design (SoC / CPU / GPU / complex ASIC environments)
• Understanding of physical design outcomes (timing, area, power trade-offs)
• Awareness of verification methodologies and design-for-test considerations
• Experience working across cross-functional teams (architecture, verification, physical design)
• Ability to operate at Principal level with autonomy and technical leadership
• Strong communication skills, both technical and non-technical

Nice to Have:

• GPU / CPU / AI accelerator experience
• Memory / cache / interconnect design
• Datapath / ALU / compute architecture experience
• Experience within high-performance or complex SoC environments

What this isn’t:

• Not a pure RTL “coding” role without ownership
• Not a narrow block-level implementation position
• Not a research-only or theoretical architecture role
• Not a role where requirements are fully defined for you

Why This Role:

• Opportunity to operate at true Principal level with ownership
• Direct impact on delivery across high-value IP programmes
• Work on complex, high-performance GPU / AI compute designs
• Strong engineering environment with cross-functional collaboration
• Exposure to architecture, design, and system-level challenges
• Immediate need — your impact will be visible quickly

Salary and Package:

• £95,000 – £110,000 base salary
• 30% Bonus (company performance related)
• Pension
• Private medical
• Life assurance
• Income protection
• Relocation support available
• Hybrid working (3 days onsite)

Interview Process:

My client can offer a 3-stage process consisting of:

• 1st stage: Technical screening (45 minutes)
• 2nd stage: Technical panel (2 hours 10 minutes)
• 3rd stage: HR / final discussion

This process can typically be completed within 2–3 weeks (depending on availability)