Contract Principal Design Engineer (SystemVerilog / Micro-Architecture) – Cambridge / Bristol / South East UK (Hybrid) – £75–£85/hr (Outside IR35)

My client’s engineering team is looking to engage Contract Principal Design Engineers to support delivery of GPU / AI compute IP.

This role is focused on immediate design capability uplift, where design is currently the constraint on programme delivery.

You’ll operate across micro-architecture and RTL, working closely with verification and physical design teams to keep projects moving.

Contract Principal Design Engineer – Role & Responsibilities:

• Define and implement micro-architecture from high-level specs
• Develop SystemVerilog RTL aligned to PPA targets
• Work with verification teams to ensure design-for-test efficiency
• Collaborate with physical design on timing / area / power considerations
• Take ownership of key blocks within complex compute designs
• Support delivery across active IP programmes

Contract Principal Design Engineer – Essential Skills:

• Strong SystemVerilog RTL design experience
• Proven micro-architecture ownership
• ~15+ years in ASIC / SoC / CPU / GPU design
• Understanding of PPA trade-offs (timing, area, power)
• Awareness of verification and design-for-test
• Ability to operate independently at Principal level

Nice to Have:

• GPU / CPU / AI accelerator experience
• Memory / cache / interconnect
• Datapath / ALU design

What this isn’t:

• Not a junior or mid-level contract
• Not a pure RTL coding role
• Not a long ramp-up environment

Why This Role:

• Immediate impact on delivery-critical programmes
• Complex, high-performance silicon work
• Strong technical environment
• Fast-moving engagement

Contract Details:

• £75–£85 per hour
• Outside IR35 (expected)
• Initial 6 months (likely extension)
• Hybrid: 3 days onsite
• Cambridge / Bristol / South East UK

Interview Process:

• Technical screening
• Technical interview

Process typically completed within 1–2 weeks