Contract Formal Verification Engineers – up £67 per hour (Inside IR35) – Oxford
Due to our continued growth, our semiconductor client is looking for an Contract Formal Verification Engineer to join their cutting-edge SoC team in the development of ASICs on an initial 6month contract basis. The successful candidate will be working with experts in different aspects of SoC development on state of the art projects.
Formal Verification Engineers Expected contributions:
- Understanding of different parts of the design & verification cycle.
- Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal).
- Working on high volume data centre & enterprise products used by industry leading Companies.
- Experience of working on projects with teams located internationally.
Formal Verification Essential qualifications and skills:
- 10+ years of digital ASIC design and verification experience
- Experience of Formal Verification (Jasper Gold or VC_Formal)
- Practical experience of:
- Translating design requirements into RTL
- Deriving functional requirements for verification
- Systemverilog UVM test benches
- Scripting languages & REST API’s (e.g. Perl/Python/TCL)
- Team player with good verbal and written communication skills
Formal Verification Desirable skills:
- Experience using SV UVM 1800.2
- Familiarity with C/C++
- Experience with any of the following storage interfaces: SAS, PCIe, NVMe (preferred) or SATA
Rate:
- up £67 per hour (Inside IR35)
- Length of Contract rolling 6 month contract (likely 12-18months in length)
- Hybrid working – 3 Days a week on site
My client can offer a 2 stage process: 1st a 30 minute call, 2nd stage is an onsite meet.
